LAYER 03 ADVANCED PACKAGING μm stack height · mm shoreline
Why packaging matters as much as the chip.
The package connects compute dies to HBM through substrates, bridges, and interposers. Those layers determine bandwidth and yield.
CoWoS-L
binding process
4
dies / package
13 mm
HBM shoreline
~6 mo
lead time
μm stack height · mm shoreline
Advanced packaging capacity determines how many compute dies can be paired with HBM at scale.
FIG. L03 · SIGNATURE PACKAGING CoWoS-L CROSS-SECTION
What this layer does
Packaging is where separate silicon pieces become a working accelerator. It sets the physical distance between logic and memory, the number of connections between them, and how large the final package can become.
That is why “packaging” is too easy to underestimate. At the high end, it is closer to system architecture than to mere enclosure design.
Read the architecture
The package is where separate dies start behaving like one machine.
The figure above shows a cross-section. The deeper lesson is architectural: modern AI hardware depends on how well the package shortens distances, raises routing density, and keeps the assembly buildable at scale.
Keep logic and memory close.
Advanced packages place compute dies and HBM near each other so far more data can move over a very short path.
Create denser wiring than the board can provide.
Interposers, bridges, and redistribution layers act like local highways between dies before signals ever reach the package edge.
Turn chiplets into one manufacturable product.
The package has to balance yield, routing, power delivery, assembly flow, and test before “multiple dies” become a shippable accelerator.
CoWoS
Large shared wiring plane under logic + HBM
TSMC’s CoWoS family uses interposer-based integration for high-performance systems. CoWoS-L adds redistribution layers plus local silicon interconnects for flexible die-to-die and logic-to-HBM connections.
EMIB
Small silicon bridges where dense links are needed
Intel’s EMIB embeds silicon bridges in the package substrate, connecting complex dies side by side without requiring one large silicon interposer underneath the whole assembly.
Foveros Direct
Vertical die stacking for shorter, denser links
Intel positions Foveros Direct as 3D stacking on an active base die using hybrid bonding for very high density, low-resistance chiplet connections.
The substrate, not the assembly, is the better business
Strip the headline names away and the back-end stack inverts. Amkor’s FY2025 10-K, filed 2026-02-20, reports a 14.0% gross margin on $6.71 billion of net sales, and the company guides 2026 capex to $2.5–3.0 billion to chase HBM-era advanced packaging. Ibiden’s FY2025 consolidated results, released 2026-05-11, show roughly 31.6% gross margin on ¥416.2 billion of net sales for the ABF substrate beneath that same package.
Amkor and Ibiden sit on opposite sides of the same accelerator — one assembles it, the other supplies the board it lands on — and the upstream component earns roughly twice the gross margin of the downstream assembler. That ratio is the clearest signal that scarcity in this layer lives in the substrate, not on the OSAT floor.
The bonding tools sit upstream of every HBM stack and CoWoS interposer
ASMPT’s Q1 2026 results, released 2026-04-22, show HK$3,966.8 million of continuing-operations revenue at a 39.5% gross margin, with bookings of HK$5,673.4 million — a 1.43 book-to-bill and the highest quarterly booking total in four years. Management attributed the surge to AI-driven demand for thermo-compression bonding, photonics and co-packaged optics, and flip-chip tools. Q2 guidance of US$540–600 million implies roughly 37% year-on-year growth at the midpoint.
Kulicke & Soffa’s Q2 FY2026 release, dated 2026-05-06, posts $242.6 million of revenue at a 49.3% gross margin, up from $162.0 million a year earlier. Q3 guidance steps to about $310 million. The company raised FY2026 capex to roughly $22 million specifically to expand TCB system production toward a $400 million annual run-rate.
Both numbers describe the same physical fact: without these bonders, HBM stacks cannot be built and CoWoS interposers cannot be populated. The OSAT-and-substrate framing misses the tool layer that sets the ceiling for everything downstream.
The OSAT floor is not flat — ASE has both scale and margin over Amkor
ASE Technology’s FY2025 Form 20-F, filed 2026-04-01, reports NT$645.4 billion of revenue at a 17.7% gross margin — roughly three times Amkor’s $6.71 billion and almost four points of margin above Amkor’s 14.0%. The Q1 2026 release of 2026-04-29 widens the gap: NT$173.7 billion of group revenue at 20.1% gross margin, up 17% year-on-year.
Inside that result, the ATM segment — packaging and test, the comparable line to Amkor — ran NT$112.4 billion of net revenue at a 26.0% gross margin, up 30% year-on-year. Management guided Q2 ATM revenue up 9–11% quarter-on-quarter and ATM gross margin to 26–27%.
ASE earns nearly twice Amkor’s gross margin on roughly three times the revenue. The advanced-packaging mix that drove that ATM result is the same allocation that decides who builds the next accelerator generation.
The chip may get the headline, but the package decides how much of it can be used.