LAYER 02 WAFER FABRICATION 858 mm² · % yield
How many useful accelerator dies fit on one wafer?
A 300 mm wafer offers many candidate reticle sites, but edge exclusion and defects reduce the number of good large dies.
75
good dies / wafer
300 mm
wafer diameter
20
EUV mask layers
858 mm²
reticle area
858 mm² · % yield
Wafer economics depend on how many large dies survive edge loss and defects.
FIG. L02 · SIGNATURE WAFER 144 SLOTS · 75 DIES
What this layer does
A wafer is not a blank spreadsheet of perfect chip sites. Die size, reticle limits, edge exclusion, and defects all reduce the number of shippable dies. That is why yield belongs in the main story, not only in a finance appendix.
The right mental model is not “one wafer equals one fixed number of chips.” It is a narrowing funnel: candidate positions first, then geometric losses, then process losses, then electrical test.
Read the yield math
A wafer begins with slots. Cost depends on survivors.
The signature figure is easier to read once the arithmetic is explicit: wafer economics move from “how many places could a die go?” to “how many good dies actually remain?”
144
Start with candidate placements.
A 300 mm wafer can fit many projected chip fields before economics enters the picture.
-32
Geometry removes incomplete dies.
Large accelerator shapes do not pack cleanly at the wafer edge, so partial sites never become products.
-32
The rim is treated as lower quality.
Edge exclusion protects yield by discounting the outer band where processing is less forgiving.
-5
Testing removes the weak survivors.
Some remaining dies fail electrical grading or cannot meet the target performance bin.
75
This is the number that pays the bill.
The wafer only becomes valuable through the dies that survive geometry, process loss, and test.
144 - 32 - 32 - 5 = 75
The chapter’s figure is not decoration. It is the cost logic of a large die.
Fewer rectangles fit, so every defect hurts more.
More good die amortize the same wafer cost.
More candidate sites stay in play before test.
The same wafer earns wildly different margins
The geometric funnel is universal: 300 mm of silicon, the same reticle stepper, the same 2 mm edge ring. The economics are not. TSMC’s FY2025 annual report posts a 59.9% gross margin on US$122.42bn of revenue, and 1Q26 widened that to 66.2% as 7 nm and below reached 74% of wafer revenue.
Intel’s Q1 FY2026 release reports a 39.4% GAAP gross margin and a US$3.1bn operating loss on the same kind of funnel. SMIC, held to DUV after export controls, posts a 20.1% gross margin on US$2.51bn in 1Q26. Three foundries, the same wafer shape, three different price-per-good-die regimes.
Read the signature figure alongside the income statement. Yield engineering decides how many of the 75 dies survive. Node leadership decides what each surviving die can charge.
Capex per good die is the leading-edge tax
One reticle shape, very different capital behind it. TSMC’s 4Q25 release set a FY2026 capex budget of US$52–56bn against FY2025 revenue of US$122.42bn, and 1Q26 alone consumed US$11.1bn. Intel’s Q1 FY2026 10-Q shows US$4.963bn of gross capex on US$13.577bn of revenue — roughly 37 cents on the dollar.
The mature-node disc is built on a thinner wallet. UMC guided FY2026 capex to US$1.5bn in its 1Q26 release. GlobalFoundries spent US$312 M on PP&E and intangibles in Q1 against US$1.634bn of revenue.
That gap explains the gross-margin gap mechanically. Leading-edge fabs amortize an EUV stack across a smaller good-die count and charge for it. Mature foundries amortize a depreciated DUV line and price to it.
The mature-node fork — same wafer, different business
UMC and GlobalFoundries run the same 300 mm disc into PMICs, RF, automotive analog, and industrial silicon. UMC’s 1Q26 release posts a 29.2% gross margin at 79% utilization, with 22/28nm contributing 34% of revenue. GlobalFoundries’ 1Q26 6-K posts a 27.6% gross margin and an 11.0% operating margin, against a FY2025 gross margin of 24.9%.
No EUV bill, no leading-node ASP. The margins land far below TSMC’s 66.2%, but they are stable, dividend-paying, and tied to industrial and automotive demand rather than the AI accelerator cycle.
The wafer layer is not one market. Two structurally different businesses share the same disc, the same edge ring, and the same 144 reticle slots. The signature figure shows the geometry; the income statement shows the divergence.
The cost of one accelerator starts with how much of the wafer survives the trip to packaging.