CHIPS.SANJAY920.COM FIELD GUIDE v0.1
From tin droplets in San Diego to gigawatt data centers in West Texas — a field guide to every layer of the GPU supply chain, every binding constraint, and every bet on the table between now and 2030.
3.5
EUV tools / GW
the ratio that sets the ceiling
20–30 GW
annual EUV flow
70–100 tools / yr ÷ 3.5 tools / GW
20×
Hopper → Blackwell
real-world inference speedup
$13 B
yearly rent / GW
at current market pricing
LIVE STATUS THE SUPPLY CHAIN RIGHT NOW
HBM bandwidth depends on how much memory interface fits around the package.
HBM4 stack prices have tripled in twelve months. SK Hynix and Samsung are sold out through Q3 2027 on three-year contracts. New DRAM fabs from 2025 decisions don’t produce meaningful capacity until late 2027.
TL;DR THE NUMBERS THAT MATTER
Twelve numbers anyone who follows this industry should be able to recall. Read this first; everything below is derivation.
3.5
EUV tools / GW
the ratio that sets the ceiling
Calc 1 GW of AI capacity ÷ ~285 MW served per EUV tool ≈ 3.5 tools
20–30 GW
annual EUV flow
70–100 tools / yr ÷ 3.5 tools / GW
Calc 70–100 EUV tools shipped / yr ÷ 3.5 tools / GW ≈ 20–29 GW / yr
$13 B
yearly rent / GW
at current market pricing
Calc 1 GW ≈ 1M GPUs × $3 / GPU-hour × 8,760 hours / yr × 50% utilization ≈ $13 B / yr
2.5 TB/s
HBM4 stack bandwidth
per 13 mm of chip edge
Calc 8 channels × 256 IO / channel × 10 GT/s ÷ 8 bits / byte ≈ 2.5 TB / s
30%
of capex → memory
hyperscalers, 2026
Calc ~$180 B hyperscaler memory spend ÷ ~$600 B big-four capex ≈ 30%
$600 B
big four capex 2026
AWS · Google · MSFT · Meta
Calc MSFT $190 B + GOOGL $185 B + AMZN $128 B + META $135 B ≈ $638 B (headline rounded down)
§ 01 THE STACK
The site follows the physical route of AI compute: light, wafers, packages, memory, accelerators, racks, data centers, cloud economics, and finally the model experience users see.
9
From EUV light at the top to the model users touch at the bottom.
HBM Memory
The layer where the chain breaks first this quarter — tracked in § 02.
§ 01b THE GUIDE DEEP-DIVE EXPLAINERS
Each section below introduces one layer, one figure, and the main constraint that shapes it.
Extreme ultraviolet lithography is the light-based machine step that prints the smallest chip patterns.
A laser strikes tin droplets to make 13.5 nm light. That light prints the smallest features on advanced logic chips.
λ 13.5 nm · watts
Tool output is limited by how many EUV scanners can be built and qualified each year.
A polished silicon disc is patterned into many individual chip dies, but not all of them survive.
A 300 mm wafer offers many candidate reticle sites, but edge exclusion and defects reduce the number of good large dies.
858 mm² · % yield
Wafer economics depend on how many large dies survive edge loss and defects.
This is the assembly step that joins separate silicon pieces and memory into one fast compute package.
The package connects compute dies to HBM through substrates, bridges, and interposers. Those layers determine bandwidth and yield.
μm stack height · mm shoreline
Advanced packaging capacity determines how many compute dies can be paired with HBM at scale.
High Bandwidth Memory is stacked DRAM placed beside the chip so data can reach it quickly.
Stacked DRAM, a base die, and thousands of IO lines add up to the bandwidth modern accelerators depend on.
GB/s · TSVs · 12-high
HBM bandwidth depends on how much memory interface fits around the package.
This is the main compute silicon that performs the heavy parallel math behind AI workloads.
The accelerator is no longer just one rectangle of silicon. It is a tightly integrated package of logic, memory interfaces, and die-to-die links.
transistors · tFLOPS
Large accelerators are constrained by reticle area, package layout, and the yield of multi-die assembly.
A rack wires many accelerator trays together so they can behave more like one larger system.
NVL72 combines compute trays, switches, copper links, power, and cooling into a rack-scale training unit.
GPUs / pod · NVLinks
Rack-scale performance depends on how many GPUs can communicate as one coherent system.
This is the building-scale layer: substations, power conversion, cooling, and deployment timing.
As racks get denser, data-center design shifts from floor space to substations, conversion losses, and cooling.
MW · PUE
New AI capacity depends on power delivery, interconnect timing, and cooling infrastructure.
This layer turns expensive servers into rented compute capacity with a payback clock attached.
This layer connects spending on compute infrastructure to rental pricing, utilization, and payback time.
$ / hr-Hopper · depreciation
Cloud economics depend on capex, utilization, pricing, and how quickly hardware depreciates.
Infrastructure cost finally becomes model training, inference, and the price of serving tokens.
The lab is where the hardware supply chain turns into a user-facing service, with compute cost flowing into every token served.
tokens / s · gross margin
At the end of the supply chain, token economics are shaped by inference efficiency and compute cost.
§ 02 BOTTLENECKS
Every twelve to eighteen months, the binding constraint on AI compute moves to a different layer of the stack. Knowing where it will sit next is the difference between a great compute contract and a bad one.
Read each column as a year: packaging was yesterday’s constraint, memory is today’s, EUV and power are tomorrow’s.
EUV
100 / yr · ASML cap
WAFER
75 wph · N3
PACKAGING
CoWoS-L · TSMC cap
HBM
12-hi · 2.5 TB/s
ACCELERATOR
Multi-die package
SCALE-UP
NVL72 · 72 GPU
DATA CENTER
20 GW / yr · US
CLOUD
$480B → $57B · 8×
EUV Lithography
Wafer Fabs
Packaging (CoWoS)
HBM Memory
GPU Die
Scale-up Rack
Data Center
Power
CoWoS bottleneck.
TSMC’s chip-on-wafer-on-substrate line was capped at a few thousand units a month while NVIDIA H100 demand quintupled. Every shipment delayed.
Long context met memory.
KV caches read on every token, sparse MoE multiplying memory demand, smartphones bidding for the same DRAM wafers. SK Hynix tripled HBM prices.
ASML capacity binds.
At ~70–100 tools/year and 3.5 tools per gigawatt, the simple flow math supports only ~20–30 GW/yr of new AI capacity before stock, allocation, and node assumptions. The end-of-decade ceiling shows up here first.
Grid won’t connect you.
Interconnection queues stretched to seven years in PJM. Turbine deposits all booked. Behind-the-meter gas became the standard answer.
§ 03 OPEN HYPOTHESES
Specific, dated, falsifiable claims about which constraints will bind, which players will surprise, and which conventional wisdoms break by 2030. Each carries a confidence label; the “non-consensus” tag marks claims where mainstream supply-chain analysis disagrees.
DRAM fabs take two years to build and the memory makers only started building in 2025. Even with smartphone volumes halving, HBM demand outruns supply.
At 70–100 EUV tools/year and 3.5 tools per gigawatt, simple annual flow is ~20–30 GW/year before installed-base, allocation, and node assumptions. Any larger ceiling needs an explicit stock model.
Already squeezed off N3 majority. By A16 the first customer is AI, not iPhone. TSMC’s focus follows margin, and AI clears every bar.
Models that run on Hoppers got smarter and cheaper to serve. The depreciation cycle is longer than five years, not shorter, so the bear thesis that Hopper-class compute is rapidly worth less does not hold.
Working tools in labs by end of decade. Mass-production hell takes another 5–7 years. China’s real catch-up is in DUV and packaging.
Free power saves 10–15% of TCO. Six months of deployment delay costs more. While chips are the bottleneck, earth wins.
Long-horizon planning batches in data centers; only reflexes run on-board. Centralized intelligence drives decentralized motion.
If revenue compounds fast enough that the next model is built on the last one’s gross margin, the West’s dispersed supply chain wins. If not, China’s vertically integrated one does.
§ 04 CHINA & TAIWAN
≈90%
made on a single island
Roughly nine-tenths of the world’s leading-edge logic comes from Taiwan. The tools that make it use chips that are also made in Taiwan — a snake eating its own tail.
In the high-growth scenario where Taiwan remains available, annual AI compute buildout can be modeled in the hundreds of gigawatts. If something goes wrong on the island, the same scenario collapses to perhaps 10–20 GW of annual new capacity — the limit of what Intel and Samsung can produce. Existing capacity continues but the growth curve stops, and the supply chain takes a decade to rebuild without Taiwan’s know-how.
Huawei is interesting precisely because it is verticalized: fabs (SMIC), networking, software, talent, AI researchers, end-market — the whole stack in one country. If Huawei had TSMC access, the consensus argument runs, they would be NVIDIA’s biggest competitor. They don’t, and they’re still building anyway.
Roughly 10×–20× less annual new capacity. Existing fleet keeps running; new growth stalls until Arizona, Korea, and Japan rebuild the missing capacity. Best estimates: a decade.
§ 05 GEOGRAPHY
12
The supply chain looks global on a map and concentrated on a list. Every critical layer above traces back to a handful of campuses in a handful of cities.
ASML EUV lithography tools
Carl Zeiss projection optics (18 mirrors per tool)
Cymer (ASML) EUV source — the tin-droplet laser
ASML reticle stages (9 G mechanical scanning)
TSMC N3 / N2 fabs and CoWoS packaging
SK Hynix HBM stacks (NVIDIA’s primary supplier)
Samsung DRAM + HBM + Foundry
Micron HBM stacks (Idaho HQ, JP fab)
Intel 18A fabs (the US backstop bet)
NVIDIA GPU + system design (no fabs)
Huawei Ascend, SMIC fabs (DUV only)
Victory Giant PCBs for the entire industry
§ 06 CAST OF CHARACTERS
12
The people you should know by name. Each plays a role no one else can, on a campus most readers couldn’t place on a map.
Builds the hardest machine humans make. Without ASML, the modern world stops.
Ninety percent of leading-edge logic. NVIDIA’s, Apple’s, AMD’s, and Google’s chips all start here.
Designs the accelerator everyone else buys. Doesn’t own a fab. Owns the customer.
Was memory’s runner-up. Picked HBM early. Is now NVIDIA’s most important external supplier.
The only vertical empire — fabs, networking, AI talent, end markets — all in one country. Sanctioned. Still climbing.
Has had in-house silicon since 2015. Has the largest scale-up domain in the world. Just woke up to AGI.
$4 B → $6 B added in two months. Now compute-constrained on every dimension simultaneously.
Signed deals with every NeoCloud that would have them. Now the largest commercial compute buyer on Earth.
~1,000 artisans polishing the eighteen multilayer mirrors that go into every EUV tool. Sub-nanometer accuracy, by hand.
From flare-gas Bitcoin to OpenAI’s biggest data-center partner. Pioneered behind-the-meter at gigawatt scale.
OpenAI’s landlord. Also the cloud half of “foundry”. Stuck navigating between the two largest customers of AI.
Trainium 3 ships this year. The only hyperscaler trying to design its own AI silicon at scale outside of Google.
§ 07 TRACE A GPU SUPPLY-CHAIN WALK
Follow a single accelerator across eight stops, twelve companies, and roughly fourteen weeks of physical motion.
Worldwide
Quartz mines in NC, Spruce Pine and elsewhere.
Japan
Shin-Etsu and SUMCO grow 30 cm boules.
Taiwan
TSMC fab in Hsinchu · 70-mask process.
Netherlands → TW
20 EUV layers from ASML tools at TSMC.
Taiwan
4 dies bonded to interposer, then to substrate.
Korea
8 stacks from SK Hynix Icheon. The big ticket.
TW · US
ASE / Amkor verify every chip at full clock.
TW → US
Wiwynn / Foxconn integrate 72 GPUs + NVLink switch.
≈14 weeks
sand → powered rack
8 stops
physically traversed
12 firms
contribute to one chip
modeled
unit cost · product-specific
3 countries
hold single points of failure